1. Field of the Invention
The present invention generally relates to delay line technology, and more particularly to a method and system utilizing a precision delay line. The invention can be applied in any system using timing signals, or data communication and transmission.
2. Description of the Prior Art
A variety of electronic devices, such as computers, monitors, flat panel displays, wireless communication devices, cellular phones, high speed two-way digital transceivers, and paging devices, to name just a few, utilize a plurality of timed signals, e.g., clock signals, vertical-synch and horizontal-synch signals, spread spectrum and digital wireless communication signals, etc., that are typically synchronized with other signals associated with such devices. A selectable delay circuit is commonly a key component of a synchronization function, such as may be part of a frequency synthesizer or a phase-locked loop circuit or other timed signal circuit. The propagation of timed electrical signals through transmission lines therefore sometimes calls for a selectable signal delay.
High precision adjustments in the frequency or phase of signal output from such synchronization function may depend on very expensive, custom analog circuit design and components. Additionally, such circuits often operate only within very narrow frequency ranges and can encounter inherent circuit startup problems or accuracy problems. This is especially problematic as the frequency of signals increases to operate with very high speed signaling circuits as found in modern devices, for example, such as radio frequency receiver circuits and transmitter circuits, and high speed clocking circuits, etc.
FIG. 1 illustrates a typical delay line 100 including delay elements 110, 114, 118, 122, 126. An input 102 provides a clock input signal to the delay line 100. An output 104 provides an output clock signal. Each of the delay elements 110, 114, 118, 122, 126, has an output electrically coupled to the next delay element stage and to a strobe output for the particular delay element. For example, see the output strobe lines 112, 116, 120, and 124. The timing of strobe (1) through strobe (N), 112, 116, 120, and 124, typically should be evenly distributed within a clock cycle from the input line 102 to the output line 104. A bias control circuit regulates the speed of the delay elements. A bias current input 106, in this example, provides the biasing current to regulate the speed of the delay elements 110, 114, 118, 122, 126. For an ideal condition, the phase difference between signal in 102 and signal out 104 is exactly one period. The delay line 100 normally has the advantage of high bandwidth and is a popular architecture for data recovery. As circuit designs push into higher clock frequency, many of the phase errors experienced in the conventional delay line 100 are no longer tolerable.
FIG. 2 shows a conventional open loop delay line architecture 200. A voltage controlled oscillator (VCO) 216 is used to set a delay line 202 propagation delay between a clock input 204 to a delay line output 206. The delay line 202 only has an input from CLK in 204 and the delay line output G(1) 206 is not fed back to the VCO 216 and control loop. A series of strobe output lines 218 provide strobe output signals Strobes(1:N). A phase and frequency detector (PFD) 208 has inputs from the CLK in 204 and from the VCO 216, but not from the delay line 202. The PFD 208 has output signals, at point H, electrically coupled to inputs of a Charge Pump circuit 210. The inputs control whether the Charge Pump 210 increases, or decreases, a voltage output, at point J. The voltage output signal of the Charge Pump 210 may contain A.C. ripple signals on top of a D.C. voltage signal. Therefore, a Filter 212, typically comprising a low pass filter, removes the A.C. ripple signals from the D.C. signal. The output of the Filter 212, at point K, is electrically coupled to the input of a Voltage-to-Current Converter 214. The output 215 of the Converter 214 is electrically coupled to an input of the VCO 216 to provide the closed loop feedback signal for the VCO 216. The output 215 of the Converter 214 is also electrically coupled to the Delay Line 202 to provide a Bias current input for the Delay Line 202. This Bias current regulates the speed of the speed of the delay elements, such as discussed earlier with respect to FIG. 1.
This circuit implementation 200 suffers from the following main disadvantages.
(1) Any mismatch between the VCO 216 and the delay line circuit 202 causes the strobe output signals from the strobe output lines 218 shift in timing positions and to lose data recovery accuracy. This is a major drawback relating to this delay line architecture 200.
(2) A mismatch within the delay line cells (i.e., between the delay line elements—such as shown in FIG. 1) causes a sampling shift between the delay line cells.
FIG. 3 shows a conventional closed loop delay line architecture 300. This circuit includes a conventional delay line 302 with delay line output G(2) 306 feeding into the input of a phase frequency detector (PFD) 308. The clock input 304 is electrically coupled an input of the delay line 302 and to an input of the PFD 308. The output of the PFD 308, at point H, is electrically coupled to the Charge Pump 310 and controls whether the voltage signal at the output of the Charge Pump 310, at point J, increases or decreases. This voltage signal, at point J, is fed through a Filter 312, preferably comprising a low pass filter, to remove ripple voltage signals from the voltage output signal from the Charge Pump 310. The filtered D.C. voltage signal from the Charge Pump 310, at point K, is electrically coupled to the input of a Voltage-to-Current Converter 314 to provide a corresponding current signal. This current signal at the output of the Voltage-to-Current Converter 314, at point L 315, is electrically coupled to the bias input of the Delay Line 302 to provide bias current to the delay line elements thereby controlling the speed of the delay line elements and corresponding strobe signal outputs at the strobe lines Strobes(1:N) 307. The speed of the delay line elements adjusts the time delay from the clock input 304 to the Delay Line signal output G(2) 306 through the delay line 302. This conventional closed loop delay line circuit implementation 300 suffers from the following disadvantages.
(1) As shown in FIGS. 4, 5, and 6, the timing diagrams illustrate potential start up problems that could cause a wrong edge to be used in the Phase Detector 308 for phase error reduction. Hence, the Phase Detector 308 can miss a strobe position window entirely. An additional digital circuit is needed to overcome this problem. This adds significant cost and additional real estate to an integrated circuit. Since integrated circuits are continuously under pressure for miniaturization and cost reduction, this disadvantage of the conventional circuit can be detrimental to commercial viability of an integrated circuit implementation.
(2) A phase error can be generated in the Phase Detector PFD 308 and the Charge Pump 310 thereby causing a strobe position shift problem. This is especially critical in wide frequency applications where accurate timing and phase must be maintained over a wide range of frequencies.
(3) The conventional closed loop delay line architecture 300 does not provide inter delay element mismatch compensation. This is especially problematic for a manufacturing process that must maintain very accurate matching of delay elements. Unfortunately, this increases the cost of manufacturing, for example, an integrated circuit and thereby reduces the commercial viability of an integrated circuit implementation.
FIGS. 4, 5, and 6, as discussed above, illustrate timing issues with the conventional closed loop delay line architecture. Specifically, for delay line architectures, the delay line output G could have the following two cases.
First, as shown in FIG. 2, the signal output G(1) 206 remains open. This open loop architecture experiences many problems as discussed above.
Second, as shown in FIG. 3, the signal output G(2) 306 is electrically coupled to the Phase Detector PFD 308 in a closed loop architecture 300. Three cases of signal timing will be briefly discussed in view of the closed loop architecture 300.
Case (1)—Ideal Correct Timing Maintained. (See FIG. 4)
G(2) output 306 is locking to the previous CLKin signal 304 clock edge. This provides one full clock period for the delay line 302 to generate correct strobes 307. This is the ideal condition. Unfortunately, actual circuit implementations can result in problems with attempting to provide evenly spaced strobe signals from the closed loop delay line architecture 300, as will be discussed below.
Case (2)—Incorrect Timing Due To Delay Line Too Fast. (See FIG. 5)
However, the Phase Detector PFD 308 could pick up transition edges for the same clock cycle for CLKin 304 & G(2) 306. As shown in FIG. 5, the Phase Locked Loop PLL 300, indicated by the circuit loop including circuit segments G(2) 306, H, J, K, and L 315, is trying to speed up the loop to reduce the CLKin 304 and the G(2) 306 phase error. This can not be achieved, unfortunately, since there are circuits involved in the delay line 302 compared to CLKin 304. It causes the Charge Pump 310 to pump the Filter voltage, at point K, to an upper voltage limit of VCC. The delay line strobes 307 therefore are not correctly setup.
Case (3)—Incorrect Timing Due To Delay Line Too Slow. (See FIG. 6)
On the other hand, the Phase Detector PFD 308 can lock at one-half, one-third, or one-fourth, of the input clock frequency at the clock input 304. This causes strobes 307 to overlap each other and consequently not be evenly distributed. This is a problem for maintaining accurately spaced strobe signal positions.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above. Improved delay line circuit architectures in systems are necessary to meet the challenging requirements of modern high speed signaling implementations, such as operating over a wide frequency range, while responding to the continuous pressures for lower cost and smaller real estate for any circuit implementation.